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integrated silicon solution, inc. www.issi.com 1-800-379-4774 1 rev. c 05/09/12 copyright ? 2012 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances is65lv256al is62lv256al features ? high-speed access time: 20, 45 ns ? automatic power-down when chip is deselected ? cmos low power operation 17 w (typical) cmos standby 50 mw (typical) operating ? ttl compatible interface levels ? single 3.3v power supply ? fully static operation: no clock or refresh required ? three-state outputs ? industrial and automotive temperatures available ? lead-free available description the issi is62/65lv256al is a very high-speed, low power, 32,768-word by 8-bit static ram. it is fabricated using issi 's high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 15 ns maximum. when ce is high (deselected), the device assumes a standby mode at which the power dissipation is reduced to 150 w (typical) with cmos input levels. easy memory expansion is provided by using an active low chip enable (ce). the active low write enable (we) controls both writing and reading of the memory. the is62/65lv256al is available in the jedec standard 28-pin soj, 28-pin sop, and the 28-pin tsop (type i) package. 32k x 8 low voltage cmos static ram functional block diagram a0-a14 ce oe we 32k x 8 memory array decoder column i/o control circuit gnd vdd i/o data circuit i/o0-i/o7 may 2012
2 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. c 05/09/12 is65lv256al is62lv256al pin configuration 28-pin soj/ 28-pin sop 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 oe a11 a9 a8 a13 we vdd a14 a12 a7 a6 a5 a4 a3 a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vdd we a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 pin configuration 28-pin tsop pin descriptions a0-a14 address inputs 1 chip enable input 51 output enable input 01 write enable input i/o0-i/o7 input/output v dd power gnd ground truth table mode ve re .e i/o operation v dd current not selected x h x high-z i sb 1 , i sb 2 (power-down) output disabled h l h high-z i cc 1 , i cc 2 read h l l d out i cc 1 , i cc 2 write l l x d in i cc 1 , i cc 2 absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd C0.5 to +4.6 v t bias temperature under bias C55 to +125 c t stg storage temperature C65 to +150 c p t power dissipation 0.5 w i out dc output current (low) 20 ma note: 1. stress greater than those listed under absolute maximum ratings may cause perma - nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
integrated silicon solution, inc. www.issi.com 1-800-379-4774 3 rev. c 05/09/12 is65lv256al is62lv256al dc electrical characteristics (over operating range) symbol parameter test co nditions min. max. unit v oh output high voltage v dd = min., i oh = C2.0 ma 2.4 v v ol output low voltage v dd = min., i ol = 4.0 ma 0.4 v v ih input high voltage 2.2 v dd + 0.3 v v il input low voltage (1) C0.3 0.8 v i li input leakage gnd v in v dd com. C1 1 a ind. C2 2 auto. C10 10 i lo output leakage gnd v out v dd , outputs disabled com. C1 1 a ind. C2 2 auto. C10 10 notes: 1. v il = C3.0v for pulse width less than 10 ns. 2. not more than one output should be shorted at one time. duration of the short circuit should not exceed 30 seconds. operating range part no. range ambient temperature v dd is62lv256al commercial 0c to +70c 3.3v +10% is62lv256al industrial C40c to +85c 3.3v 10% is65lv256al automotive C40c to +125c 3.3v 10%
4 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. c 05/09/12 is65lv256al is62lv256al capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 5 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c , f = 1 mhz, v dd = 3.3v. power supply characteristics (1) (over operating range) -20 ns -45 ns symbol parameter test conditions min. max. min. max. unit i cc 1 v dd operating v dd = max., ce = v il com. 4 4 ma supply current i out = 0 ma, f = 0 ind. 5 5 auto. 8 i cc 2 v dd dynamic operating v dd = max., ce = v il com. 20 10 ma supply current i out = 0 ma, f = f max ind. 25 12 auto. 20 typ. (2) 15 7 i sb 1 ttl standby current v dd = max., com. 1.5 1.5 ma (ttl inputs) v in = v ih or v il ind. 1.8 1.8 ce v ih , f = 0 auto. 2 i sb 2 cmos standby v dd = max., com. 15 15 a current (cmos inputs) ce v dd C 0.2v, ind. 20 20 v in > v dd C 0.2v, or auto. 50 v in 0.2v, f = 0 typ. (2) 2 2 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 3.3v, t a = 25 o c and not 100% tested.
integrated silicon solution, inc. www.issi.com 1-800-379-4774 5 rev. c 05/09/12 is65lv256al is62lv256al read cycle switching characteristics (1) (over operating range) -20 ns -45 ns symbol parameter min. max. min. max. unit t rc read cycle time 20 45 ns t aa address access time 20 45 ns t oha output hold time 2 2 ns t ace ce access time 20 45 ns t doe oe access time 10 25 ns t lzoe (2) oe to low-z output 0 0 ns t hzoe (2) oe to high-z output 9 0 20 ns t lzce (2) ce to low-z output 3 3 ns t hzce (2) ce to high-z output 9 0 20 ns t pu (3) ce to power-up 0 0 ns t pd (3) ce to power-down 18 30 ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3.0v and output loading specifed in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. not 100% tested. ac test loads ac test conditions p arameter unit input pulse level 0v to 3.0v input rise and fall times 3 ns input and output timing 1.5v and reference levels output load see figures 1 and 2 figure 1. figure 2. 635 30 pf including jig and scope 702 output 3.3v 635 5 pf including jig and scope 702 output 3.3v
6 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. c 05/09/12 is65lv256al is62lv256al data valid t aa t oha t oha t rc d out address 50% 50% t rc t oha t aa t doe t lzoe t ace t lzce t hzoe t pd high-z t pu data valid t hzce isb address oe ce d out supply current icc read cycle no. 2 (1,3) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe, ce = v il . 3. address is valid prior to or coincident with ce low transitions. ac waveforms read cycle no. 1 (1,2)
integrated silicon solution, inc. www.issi.com 1-800-379-4774 7 rev. c 05/09/12 is65lv256al is62lv256al ac waveforms write cycle no. 1 ( we controlled) (1,2) data-in valid data undefined t wc t sce t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address ce we d out d in write cycle switching characteristics (1,3) (over operating range) -20 ns -45 ns symbol parameter min. max. min. max. unit t wc write cycle time 20 45 ns t sce ce to write end 15 35 ns t aw address setup time to write end 14 25 ns t ha address hold from write end 0 0 ns t sa address setup time 0 0 ns t pwe (4) we pulse width 14 25 ns t sd data setup to write end 13 20 ns t hd data hold from write end 0 0 ns t hzwe (2) we low to high-z output 8 20 ns t lzwe (2) we high to low-z output 0 0 ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3.0v and output loading specifed in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defned by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. 4. tested with oe high.
8 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. c 05/09/12 is65lv256al is62lv256al notes: 1. the internal write time is defned by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. 2. i/o will assume the high-z state if oe v ih . high-z data undefined data-in valid t wc t sce t sa t ha t pwe t aw t hzwe t sd t hd t lzwe address d in ce we d out write cycle no. 2 ( ce controlled) (1,2)
integrated silicon solution, inc. www.issi.com 1-800-379-4774 9 rev. c 05/09/12 is65lv256al is62lv256al data retention switching characteristics symbol parameter test condition min. typ. max. unit v dr v dd for data retention see data retention waveform 2.0 3.6 v i dr data retention current v dd = 2.0v, ce v dd C 0.2v com. 15 a v in v dd C 0.2v, or v in v ss + 0.2v ind. 20 auto. 50 typ. (1) 2 t sdr data retention setup time see data retention waveform 0 ns t rdr recovery time see data retention waveform t rc ns note: 1. typical values are measured at v dd = 3.3v, t a = 25 o c and not 100% tested. data retention waveform ( ce controlled) vdd ce vdd - 0.2v t sdr t rdr v dr ce gnd data retention mode
10 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. c 05/09/12 is65lv256al is62lv256al ordering information commercial range: 0c to +70c speed (ns) order part no. packag e 20 is62lv256al-20t tsop is62lv256al-20tl tsop, lead-free is62lv256al-20jl 300-mil plastic soj, lead-free 45 is62lv256al-45t tsop is62lv256al-45tl tsop, lead-free industrial range: C40c to +85c speed (ns) order part no. pa ckage 20 is62lv256al-20ti tsop is62lv256al-20tli tsop, lead-free is62lv256al-20jli 300-mil plastic soj, lead-free 45 is62lv256al-45ti tsop is62lv256al-45tli tsop, lead-free is62lv256al-45uli 330-mil plastic sop, lead-free automotive range: C40c to +125c speed (ns) order part no. package 45 is65lv256al-45ta3 tsop is65lv256al-45tla3 tsop, lead-free is65lv256al-45ula3 330-mil plastic sop, lead-free
integrated silicon solution, inc. www.issi.com 1-800-379-4774 11 rev. c 05/09/12 is65lv256al is62lv256al
12 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. c 05/09/12 is65lv256al is62lv256al note : 0.1 y at the seating plane after final test. 4. formed leads shall be planar with respect to one another within 0.1mm 1. controlling dimension : mm 2. dimension d1 adn e do not include mold protrusion . 3. dimension b2 does not include dambar protrusion/intrusion. 07/05/2006 package outline
integrated silicon solution, inc. www.issi.com 1-800-379-4774 13 rev. c 05/09/12 is65lv256al is62lv256al

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